1. Field of the Invention
The present invention relates to a digital/analog (D/A) converter.
2. Description of the Related Art
In a first prior art D/A converter, resistors are connected in series between a power supply voltage terminal and a ground terminal. Nodes of the resistors are connected via analog switches to an output terminal. That is, one of the analog switches is turned ON in accordance with a decoded value of a digital input data. This will be explained later in detail.
In the above-described first prior art D/A converter, however, the larger the number of bits of the digital input data, the larger the number of ladder resistors connected in series. This reduces the integration. Also, since it is substantially impossible to make the values of a large number of ladder resistors uniform, a high resolution cannot be expected.
In a second prior art D/A converter, an (m+n)-bit digital input data is divided into an upper-order m-bit data and a lower-order n-bit data which are supplied to a main D/A conversion section and a sub D/A conversion section. The analog voltages of the D/A conversion sections are supplied to a weighted adder. Thus, an output voltage corresponding to the digital input can be obtained at an output terminal. This also will be explained later in detail.
In the above-described second prior art D/A converter, since the number of bits of each of the D/A conversion sections is decreased, the total number of ladder resistors can be remarkably decreased as compared with the first prior art D/A converter. This improves the integration. Also, since it is easy to make the values of a smaller number of ladder resistors uniform, a high resolution for each of the D/A conversion sections can be expected.
In tile above-described second prior art D/A converter, however, since the analog voltage is obtained by the addition of two analog voltages, the output voltage fluctuates. Thus, the linear output characteristics are deteriorated.
In a third D/A converter (see: JP-A-9-83368), an (m+n)-bit digital input data is divided into an upper-order m-bit data and a lower-order n-bit data. The lower-order n-bit data is supplied to a pulse modulation circuit, and the upper-order m-bit data is supplied to m-bit adder. The pulse modulation circuit generates a 1-bit data corresponding to the lower-order n-bit data in synchronization with a clock signal. The m-bit adder adds the 1-bit of the pulse modulation circuit to the upper-order m-bit data to generate m-bit data which is subjected to a D/A conversion by a D/A conversion section. Then, the analog output voltage of the D/A conversion section is supplied to a low-pass filter, to remove a high frequency component of the analog output voltage. Thus, an analog output voltage corresponding to the (m+n)-bit input data is obtained. This also will be explained later in detail.
In the above-described third prior art D/A converter, since the total number of ladder resistors is decreased, the integration and the resolution can be improved. Also, since the weighted adder of the second prior art D/A converter is unnecessary, the linear output characteristics can be improved.
In the above-described third prior art D/A converter, however, the location of 1-bit data corresponding to definite lower-order bits is definite within the clock signal. As a result, when a special sequence of the lower-order bits occurs, the accuracy of conversion remarkably deteriorates.
It is an object of the present invention to provide a D/A converter having an improved conversion accuracy.
According to the present invention, in a digital/analog converter for (m+n)-bit digital input data, a sigma-delta type pulse modulation circuit receives lower-order n bits of the digital input data lo generate 1-bit data corresponding to the lower-order n bits in synchronization with a clock signal. An m-bit adder adds said 1-bit data to upper-order m bits of the digital input data. An m-bit digital/analog conversion section performs a. digital-to-analog conversion upon an output value of the m-bit adder. A low-pass filter removes a high frequency component of an output value of the m-bit digital/analog conversion section to generate an analog data corresponding to the (m+n)-bit digital input data.